With the rapid development of integrated circuit fabrication processes, cells in modern integrated circuits are fabricated in a more compact manner and have smaller pitches, as compared with cells in conventional integrated circuits. For example, pitch requirements for integrated circuit fabrication processes have evolved from micron level to nanometer level. Accordingly, lithography has to be precisely performed in order for layout patterns to be exactly exposed via masks before being mapped to a semiconductor wafer. Current lithography technique faces many unsolved problems. Smaller cell pitches increase the layout pattern distortion due to light diffraction and affect the reliability of the integrated circuit fabrication process.
Double pattern technology is commonly used to apply immerse lithography technology at a nanometer scale. Double pattern technology enables integrated circuit-based layout patterns on a single mask to be decomposed and mapped to two masks. In addition, layout patterns of finer pitches can be obtained using double exposure technology.
Double pattern lithography technology, in which layout patterns on a single mask are decomposed and mapped to two masks, can reduce layout pattern pitches; however, there remain problems with stitches. Stitches refer to the dividing points between different masks on the same sub-pattern. Stitches can degrade reliability of integrated circuit fabrication processes and reduce the printability of the layout patterns.
Stitches can also cause pattern defects such as stitching displacement or pattern short-circuiting during the fabrication process, thereby reducing the reliability of integrated circuit layouts or circuit cells. Therefore, there is a need for a monitoring pattern for double patterning, as well as for a pattern stitch monitoring method and a semiconductor wafer therewith.